View M58BW016_448453.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M58BW016BT, M58BW016BB M58BW016DT, M58BW016DB
16 Mbit (512Kb x32, Boot Block, Burst) 3V Supply Flash Memories
PE4FEATURES SUMMARY s SUPPLY VOLTAGE - VDD = 2.7V to 3.6V for Program, Erase and Read - VDDQ = VDDQIN = 2.4V to 3.6V for I/O Buffers
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Figure 1. Packages
- VPP = 12V for fast Program (optional) HIGH PERFORMANCE - Access Time: 80, 90 and 100ns - 56MHz Effective Zero Wait-State Burst Read - Synchronous Burst Reads - Asynchronous Page Reads
PQFP80 (T)
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HARDWARE BLOCK PROTECTION - WP pin Lock Program and Erase
BGA
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SOFTWARE BLOCK PROTECTION - Tuning Protection to Lock Program and Erase with 64 bit User Programmable Password (M58BW016B version only)
LBGA80 (ZA) 10 x 8 ball array
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OPTIMIZED for FDI DRIVERS - Fast Program / Erase suspend latency time < 6s - Common Flash Interface
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MEMORY BLOCKS - 8 Parameters Blocks (Top or Bottom) - 31 Main Blocks
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LOW POWER CONSUMPTION - 5A Typical Deep Power Down - 60A Typical Standby - Automatic Standby after Asynchronous Read
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ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Top Device Code M58BW016xT: 8836h - Bottom Device Code M58BW016xB: 8835h
September 2002
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TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3. LBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4. PQFP Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 8 9
Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Tuning Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 2. Top Boot Block Addresses, M58BW016BT, M58BW016DT . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Bottom Boot Block Addresses, M58BW016BB, M58BW016DT . . . . . . . . . . . . . . . . . . . 12 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Address Inputs (A0-A18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data Inputs/Outputs (DQ0-DQ31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Disable (GD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Burst Clock (K). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Burst Address Advance (B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Valid Data Ready (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output Supply Voltage (VDDQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input Supply Voltage (VDDQIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Program/Erase Supply Voltage (VPP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ground (VSS and VSSQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Asynchronous Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Asynchronous Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Asynchronous Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Asynchronous Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Asynchronous Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Automatic Low Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5. Asynchronous Read Electronic Signature Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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Synchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 6. Synchronous Burst Read Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read Select Bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 X-Latency Bits (M14-M11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Y-Latency Bit (M9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Valid Data Ready Bit (M8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Burst Type Bit (M7).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Valid Clock Edge Bit (M6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Wrap Burst Bit (M3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Burst Length Bit (M2-M0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7. Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Read Query Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Set Burst Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Tuning Protection Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Tuning Protection Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 10. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . 26 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Program Status, Tuning Protection Unlock Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Tuning Protection Status (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 12. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 13. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 7. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 8. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 14. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 15. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 9. Asynchronous Bus Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 16. Asynchronous Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10. Asynchronous Latch Controlled Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . Table 17. Asynchronous Latch Controlled Bus Read AC Characteristics . . . . . . . . . . . . . . . . . . . Figure 11. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 18. Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12. Asynchronous Write AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 13. Asynchronous Latch Controlled Write AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics . . . . . . . . . . . . . . Figure 14. Synchronous Burst Read (Data Valid from 'n' Clock Rising Edge) . . . . . . . . . . . . . . . Table 20. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 15. Synchronous Burst Read (Data Valid from 'n' Clock Rising Edge) . . . . . . . . . . . . . . . Figure 16. Synchronous Burst Read - Continuous - Valid Data Ready Output . . . . . . . . . . . . . . . Figure 17. Synchronous Burst Read - Burst Address Advance. . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 18. Reset, Power-Down and Power-up AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 21. Reset, Power-Down and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30 30 30 30 31 32 32 33 33 34 34 35 36 37 38 39 39 40 40 41 41
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 19. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Bottom View Package Outline . . . . Table 22. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Package Mechanical Data . . . . . . . . Figure 20. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline . . . . . . . . . . . . . . . . . . . . Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data. . . . . . . . . . . . . 42 42 43 43
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 25. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 APPENDIX A. COMMON FLASH INTERFACE - CFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 26. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 27. CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 28. CFI - Device Voltage and Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 29. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 30. Extended Query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 46 47 47 48
APPENDIX B. FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 21. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 22. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 50
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Figure 23. Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 24. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . Figure 25. Unlock Device and Change Tuning Protection Code Flowchart . . . . . . . . . . . . . . . . . Figure 26. Unlock Device and Program a Tuning Protected Block Flowchart . . . . . . . . . . . . . . . . Figure 27. Unlock Device and Erase a Tuning Protected Block Flowchart . . . . . . . . . . . . . . . . . . Figure 28. Power-up Sequence to Burst the Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29. Command Interface and Program Erase Controller Flowchart (a) . . . . . . . . . . . . . . . . Figure 30. Command Interface and Program Erase Controller Flowchart (b) . . . . . . . . . . . . . . . . Figure 31. Command Interface and Program Erase Controller Flowchart (c) . . . . . . . . . . . . . . . . Figure 32. Command Interface and Program Erase Controller Flowchart (d) . . . . . . . . . . . . . . . . Figure 33. Command Interface and Program Erase Controller Flowchart (e) . . . . . . . . . . . . . . . . 51 52 53 54 55 56 57 58 59 60 61
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SUMMARY DESCRIPTION The M58BW016B/D is a 16Mbit non-volatile Flash memory that can be erased electrically at the block level and programmed in-system on a DoubleWord basis using a 2.7V to 3.6V V DD supply for the circuit and a V DDQ supply down to 2.4V for the Input and Output buffers. Optionally a 12V VPP supply can be used to provide fast program and erase for a limited time and number of program/erase cycles. The devices support Asynchronous (Latch Controlled and Page Read) and Synchronous Bus operations. The Synchronous Burst Read Interface allows a high data transfer rate controlled by the Burst Clock, K, signal. It is capable of bursting fixed or unlimited lengths of data. The burst type, latency and length are configurable and can be easily adapted to a large variety of system clock frequencies and microprocessors. All Writes are Asynchronous. On power-up the memory defaults to Read mode with an Asynchronous Bus. The device has a boot block architecture with an array of 8 parameter block of 64Kb each and 31 main blocks of 512Kb each. The parameter blocks can be located at the top of the address space, M58BW016BT, M58BW016DT or at the bottom, M58BW016BB, M58BW016DB. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a Program or Erase operation can be detected and any error conditions identified in the Status Regis-
ter. The command set required to control the memory is consistent with JEDEC standards. Erase can be suspended in order to perform either Read or Program in any other block and then resumed. Program can be suspended to Read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. All blocks are protected during power-up. The M58BW016B features four different levels of block protection to avoid unwanted program/erase operations. The WP pin offers an hardware protection on two of the parameter blocks and all of the main blocks. The Program and Erase commands can be password protected by the Tuning Protection command. All Program or Erase operations are blocked when Reset, RP, is held low. The M58BW016D offers the same protection features with the exception of the Tuning Block Protection which is disabled in the factory. A Reset/Power-down mode is entered when the RP input is Low. In this mode the power consumption is lower than in the normal standby mode, the device is write protected and both the Status and the Burst Configuration Registers are cleared. A recovery time is required when the RP input goes High. The memory is offered in PQFP80 (14 x 20mm) and LBGA80 (1.0mm pitch) packages and it is supplied with all the bits erased (set to '1').
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Figure 2. Logic Diagram Table 1. Signal Names
A0-A18 DQ0-DQ7 Address inputs Data Input/Output, Command Input Data Input/Output, Burst Configuration Register Data Input/Output Burst Address Advance Chip Enable Output Enable Burst Clock Latch Enable Valid Data Ready (open drain output) Reset/Power-down Write Enable Output Disable Write Protect Supply Voltage Power Supply for Output Buffers Power Supply for Input Buffers only Optional Supply Voltage for Fast Program and Fast Erase Operations Ground Input/Output Ground Not Connected Internally Don't Use as Internally Connected
VDD VDDQ VDDQIN VPP
DQ8-DQ15 DQ16-DQ31
A0-A18 K L E RP G GD W WP B M58BW016BT M58BW016BB M58BW016DT M58BW016DB
B
DQ0-DQ31
E G K L
R
R RP W GD WP VDD VDDQ VDDQIN
VSS
VSSQ
AI04155
VPP VSS VSSQ NC DU
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Figure 3. LBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
A15
A14
VDD
VPP
VSS
A6
A3
A2
B
A16
A13
A12
A9
A8
A5
A4
A1
C
A17
A18
A11
A10
NC
A7
DU
A0
D
DQ3
DQ0
DU
DU
DU
DQ31
DQ30
DQ29
E
VDDQ
DQ4
DQ2
DQ1
DQ27
DQ28
DQ26
VDDQ
F
VSSQ
DQ7
DQ6
DQ5
NC
DQ25
DQ24
VSSQ
G
VDDQ
DQ8
DQ10
DQ9
DQ22
DQ21
DQ23
VDDQ
H
DQ13
DQ12
DQ11
WP
DQ17
DQ19
DQ18
DQ20
J
DQ15
DQ14
L
B
E
G
R
DQ16
K
VDDQIN
RP
K
VSS
VDD
W
GD
DU
AI04151b
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M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
Figure 4. PQFP Connections (Top view through package)
DU R GD WP W G E VDD B VSS L NC NC K RP VDDQIN 80 73 DQ16 DQ17 DQ18 DQ19 VDDQ VSSQ DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 VDDQ VSSQ DQ28 DQ29 DQ30 DQ31 DU A0 A1 A2 1 65
64
12
M58BW016BT M58BW016BB M58BW016DT M58BW016DB
53
25
32
VSS VPP VDD A9 A10 A11 A12 A13 A14 A15
A3 A4 A5 A6 A7 A8
AI04152b
40
24
41
DQ15 DQ14 DQ13 DQ12 VSSQ VDDQ DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 VSSQ VDDQ DQ3 DQ2 DQ1 DQ0 NC A18 A17 A16
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Block Protection The M58BW016B features four different levels of block protection. The M58BW016D has the same block protection with the exception of the Tuning Block Protection, which is disabled in the factory. s Write Protect Pin, WP, - When WP is low, VIL, all the lockable parameter blocks (two upper (Top ) or lower (Bottom)) and all the main blocks are protected. When WP is high (VIH) all the lockable parameter blocks and all the main blocks are unprotected.
s
Reset/Power-Down Pin, RP, - If the device is held in reset mode (RP at VIL), no program or erase operations can be performed on any block. Tuning Block Protection: M58BW016B features a 64 bit password protection for program and erase operations for a fixed number of blocks After power-up or reset the device is tuning protected. An Unlock command is provided to allow program or erase operations in all the blocks.
s
After a device reset the first two kinds of block protection (WP, RP) can be combined to give a flexible block protection. They do not affect the Tuning Block Protection. When the two protections are disabled, WP and RP at VIH, the blocks locked by the Tuning Block Protection cannot be modified. All blocks are protected during power-up. Tuning Block Protection. The Tuning Block Protection is a software feature to protect certain
blocks from program or erase operations. It allows the user to lock program and erase operations with a user definable 64 bit code. It is only available on the M58BW016B version. The code is written once in the Tuning Protection Register and cannot be erased. When shipped the flash memory will have the Tuning Protection Code bits set to `1'. The user can program a `0' in any of the 64 positions. Once programmed it is not possible to reset a bit to `1' as the cells cannot be erased. The Tuning Protection Register can be programmed at any moment (after providing the correct code), however once all bits are set to `0' the Tuning Protection Code can no longer be altered. The Tuning Protection Code locks the program and erase operations of 2 parameter and 24 main blocks, blocks 0, 1 and 15-38 for the bottom configuration and the blocks 0-23, 37 and 38 for the top configuration. The tuning blocks are "locked" if the tuning protection code has not been provided, and "unlocked" once the correct code has been provided. The tuning blocks are locked after reset or power-up. The tuning protection status can be monitored in the Status Register. Refer to the Status Register section. Refer to the Command Interface section for the Tuning Protection Block Unlock and Tuning Protection Program commands. See Appendix B, Figure 25, 26 and 27 for suggested flowcharts for using the Tuning Block Protection commands. For further information on the Tuning Block Protection refer to Application Note, AN1361.
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Table 2. Top Boot Block Addresses, M58BW016BT, M58BW016DT
# 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 Size (Kbit) 64 64 64 64 64 64 64 64 512 512 512 512 512 512 512 512 512 512 512 Address Range 7F800h-7FFFFh 7F000h-7F7FFh 7E800h-7EFFFh 7E000h-7E7FFh 7D800h-7DFFFh 7D000h-7D7FFh 7C800h-7CFFFh 7C000h-7C7FFh 78000h-7BFFFh 74000h-77FFFh 70000h-73FFFh 6C000h-6FFFFh 68000h-6BFFFh 64000h-67FFFh 60000h-63FFFh 5C000h-5FFFFh 58000h-5BFFFh 54000h-57FFFh 50000h-53FFFh TP(1) yes yes no no no no no no no no no no no no no yes yes yes yes # 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Size (Kbit) 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 Address Range 4C000h-4FFFFh 48000h-4BFFFh 44000h-47FFFh 40000h-43FFFh 3C000h-3FFFFh 38000h-3BFFFh 34000h-37FFFh 30000h-33FFFh 2C000h-2FFFFh 28000h-2BFFFh 24000h-27FFFh 20000h-23FFFh 1C000h-1FFFFh 18000h-1BFFFh 14000h-17FFFh 10000h-13FFFh 0C000h-0FFFFh 08000h-0BFFFh 04000h-07FFFh 00000h-03FFFh TP(1) yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes
Note: 1. TP = Tuning Protected Block, only available for the M58BW016B.
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Table 3. Bottom Boot Block Addresses, M58BW016BB, M58BW016DT
# 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 Size (Kbit) 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 Address Range 7C000h-7FFFFh 78000h-7BFFFh 74000h-77FFFh 70000h-73FFFh 6C000h-6FFFFh 68000h-6BFFFh 64000h-67FFFh 60000h-63FFFh 5C000h-5FFFFh 58000h-5BFFFh 54000h-57FFFh 50000h-53FFFh 4C000h-4FFFFh 48000h-4BFFFh 44000h-47FFFh 40000h-43FFFh 3C000h-3FFFFh 38000h-3BFFFh 34000h-37FFFh TP(1) yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes # 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Size (Kbit) 512 512 512 512 512 512 512 512 512 512 512 512 64 64 64 64 64 64 64 64 Address Range 30000h-33FFFh 2C000h-2FFFFh 28000h-2BFFFh 24000h-27FFFh 20000h-23FFFh 1C000h-1FFFFh 18000h-1BFFFh 14000h-17FFFh 10000h-13FFFh 0C000h-0FFFFh 08000h-0BFFFh 04000h-07FFFh 03800h-03FFFh 03000h-037FFh 02800h-02FFFh 02000h-027FFh 01800h-01FFFh 01000h-017FFh 00800h-00FFFh 00000h-007FFh TP(1) yes yes yes yes yes no no no no no no no no no no no no no yes yes
Note: 1. TP = Tuning Protected Block, only available for the M58BW016B.
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SIGNAL DESCRIPTIONS See Figure 2, Logic Diagram and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A18). The Address Inputs are used to select the cells to access in the memory array during Bus Read operations either to read or to program data to. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Chip Enable must be low when selecting the addresses. The address inputs are latched on the rising edge of Latch Enable L or Burst Clock K, whichever occurs first, in a read operation.The address inputs are latched on the rising edge of Chip Enable, Write Enable or Latch Enable, whichever occurs first in a Write operation. The address latch is transparent when Latch Enable is low, V IL. The address is internally latched in an Erase or Program operation. Data Inputs/Outputs (DQ0-DQ31). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation, or are used to input the data during a program operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. When used to input data or Write commands they are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. When Chip Enable and Output Enable are both low, VIL, and Output Disable is at VIH, the data bus outputs data from the memory array, the Electronic Signature, the CFI Information or the contents of the Status Register. The data bus is high impedance when the device is deselected with Chip Enable at VIH, Output Enable at VIH, Output Disable at VIL or Reset/Power-Down at VIL. The Status Register content is output on DQ0-DQ7 and DQ8DQ31 are at V IL. Chip Enable (E). The Chip Enable, E, input activates the memory control logic, input buffers, decoders and sense amplifiers. Chip Enable, E, at VIH deselects the memory and reduces the power consumption to the Standby level. Output Enable (G). The Output Enable, G, gates the outputs through the data output buffers during a read operation, when Output Disable GD is at VIH. When Output Enable G is at VIH, the outputs are high impedance independently of Output Disable. Output Disable (GD). The Output Disable, GD, deactivates the data output buffers. When Output Disable, GD, is at VIH, the outputs are driven by the Output Enable. When Output Disable, GD, is at VIL, the outputs are high impedance independent-
ly of Output Enable. The Output Disable pin must be connected to an external pull-up resistor as there is no internal pull-up resistor to drive the pin. Write Enable (W). The Write Enable, W, input controls writing to the Command Interface, Input Address and Data latches. Both addresses and data can be latched on the rising edge of Write Enable (also see Latch Enable, L). Reset/PowerReset/Power-Down (RP). The Down, RP, is used to apply a hardware reset to the memory. A hardware reset is achieved by holding Reset/Power-Down Low, V IL, for at least tPLPH. Writing is inhibited to protect data, the Command Interface and the Program/Erase Controller are reset. The Status Register information is cleared and power consumption is reduced to deep powerdown level. The device acts as deselected, that is the data outputs are high impedance. After Reset/Power-Down goes High, V IH, the memory will be ready for Bus Read operations after a delay of t PHEL or Bus Write operations after tPHWL. If Reset/Power-Down goes low, VIL, during a Block Erase, a Program or a Tuning Protection Program the operation is aborted, in a time of t PLRH maximum, and data is altered and may be corrupted. During Power-up power should be applied simultaneously to VDD and VDDQ(IN) with RP held at VIL. When the supplies are stable RP is taken to VIH. Output Enable, G, Chip Enable, E, and Write Enable, W, should be held at VIH during power-up. In an application, it is recommended to associate Reset/Power-Down pin, RP, with the reset signal of the microprocessor. Otherwise, if a reset operation occurs while the memory is performing an erase or program operation, the memory may output the Status Register information instead of being initialized to the default Asynchronous Random Read. See Table 21 and Figure 18, Reset, Power-Down and Power-up Characteristics, for more details. Latch Enable (L). The Bus Interface can be configured to latch the Address Inputs on the rising edge of Latch Enable, L, for Asynchronous Latch Enable Controlled Read or Write or Synchronous Burst Read operations. In Synchronous Burst Read operations the address is latched on the active edge of the Clock when Latch Enable is Low, VIL. Once latched, the addresses may change without affecting the address used by the memory. When Latch Enable is Low, VIL, the latch is transparent. Latch Enable, L, can remain at VIL for Asynchronous Random Read and Write operations. Burst Clock (K). The Burst Clock, K, is used to synchronize the memory with the external bus dur13/62
M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
ing Synchronous Burst Read operations. Bus signals are latched on the active edge of the Clock. The Clock can be configured to have an active rising or falling edge. In Synchronous Burst Read mode the address is latched on the first active clock edge when Latch Enable is low, VIL, or on the rising edge of Latch Enable, whichever occurs first. During Asynchronous bus operations the Clock is not used. Burst Address Advance (B). The Burst Address Advance, B, controls the advancing of the address by the internal address counter during Synchronous Burst Read operations. Burst Address Advance, B, is only sampled on the active clock edge of the Clock when the X-latency time has expired. If Burst Address Advance is Low, VIL, the internal address counter advances. If Burst Address Advance is High, VIH, the internal address counter does not change; the same data remains on the Data Inputs/Outputs and Burst Address Advance is not sampled until the Y-latency expires. The Burst Address Advance, B, may be tied to VIL. Valid Data Ready (R). The Valid Data Ready output, R, is an open drain output that can be used, during Synchronous Burst Read operations, to identify if the memory is ready to output data or not. The Valid Data Ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. Valid Data Ready, at VIH, indicates that new data is or will be available. When Valid Data Ready is Low, V IL, the previous data outputs remain active. In all Asynchronous operations, Valid Data Ready is high-impedance. It may be tied to other components with the same Valid Data Ready signal to create a unique system Ready signal. The Valid Data Ready output has an internal pull-up resistor of around 1 M powered from VDDQ, designers should use an external pull-up resistor of the correct value to meet the external timing requirements for Valid Data Ready going to V IH. Write Protect (WP). The Write Protect, WP, provides protection against program or erase operations. When Write Protect, WP, is at VIL the first two (in the bottom configuration) or last two (in the top configuration) parameter blocks and all main blocks are locked. When Write Protect WP is at VIH all the blocks can be programmed or erased, if no other protection is used. Supply Voltage (VDD). The Supply Voltage, VDD, is the core power supply. All internal circuits draw their current from the V DD pin, including the Program/Erase Controller. Output Supply Voltage (VDDQ). The Output Supply Voltage, VDDQ, is the output buffer power supply for all operations (Read, Program and Erase) used for DQ0-DQ31 when used as outputs. Input Supply Voltage (V DDQIN). The Input Supply Voltage, VDDIN, is the power supply for all input signal. Input signals are: K, B, L, W, GD, G, E, A0A18 and D0-D31, when used as inputs. Program/Erase Supply Voltage (VPP). The Program/Erase Supply Voltage, VPP, is used for program and erase operations. The memory normally executes program and erase operations at V PP1 voltage levels. In a manufacturing environment, programming may be speeded up by applying a higher voltage level, VPPH, to the VPP pin. The voltage level VPPH may be applied for a total of 80 hours over a maximum of 1000 cycles. Stressing the device beyond these limits could damage the device. Ground (VSS and VSSQ ). The Ground VSS is the reference for the internal supply voltage VDD. The Ground VSSQ is the reference for the output and input supplies VDDQ, and VDDQIN. It is essential to connect VSS and VSSQ together. Note: A 0.1F capacitor should be connected between the Supply Voltages, V DD, VDDQ and VDDIN and the Grounds, VSS and VSSQ to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during all operations of the parts, see Table 15, DC Characteristics, for maximum current supply requirements. Don't Use (DU). This pin should not be used as it is internally connected. Its voltage level can be between V SS and VDDQ or leave it unconnected. Not Connected (NC). This pin is not physically connected to the device.
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BUS OPERATIONS Each bus operations that controls the memory is described in this section, see Tables 4, 5 and 6 Bus Operations, for a summary. The bus operation is selected through the Burst Configuration Register; the bits in this register are described at the end of this section. On Power-up or after a Hardware Reset the memory defaults to Asynchronous Bus Read and Asynchronous Bus Write, no other bus operation can be performed until the Burst Control Register has been configured. The Electronic Signature, CFI or Status Register will be read in asynchronous mode regardless of the Burst Control Register settings. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Asynchronous Bus Operations For asynchronous bus operations refer to Table 4 together with the following text. Asynchronous Bus Read. Asynchronous Bus Read operations read from the memory cells, or specific registers (Electronic Signature, Status Register, CFI and Burst Configuration Register) in the Command Interface. A valid bus operation involves setting the desired address on the Address Inputs, applying a Low signal, V IL, to Chip Enable and Output Enable and keeping Write Enable and Output Disable High, VIH. The Data Inputs/Outputs will output the value, see Figure 9, Asynchronous Bus Read AC Waveforms, and Table 16, Asynchronous Bus Read AC Characteristics, for details of when the output becomes valid. Asynchronous Read is the default read mode which the device enters on power-up or on return from Reset/Power-Down. Asynchronous Latch Controlled Bus Read. Asynchronous Latch Controlled Bus Read operations read from the memory cells or specific registers in the Command Interface. The address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses. A valid bus operation involves setting the desired address on the Address Inputs, setting Chip Enable and Latch Enable Low, V IL and keeping Write Enable High, VIH; the address is latched on the rising edge of Latch Enable. Once latched, the Address Inputs can change. Set Output Enable Low, VIL, to read the data on the Data Inputs/Outputs; see Figure 1, Asynchronous Latch Controlled Bus Read AC Waveforms and Table 17, Asynchronous Latch Controlled Bus Read AC Characteristics for details on when the output becomes valid.
Note that, since the Latch Enable input is transparent when set Low, VIL, Asynchronous Bus Read operations can be performed when the memory is configured for Asynchronous Latch Enable bus operations by holding Latch Enable Low, VIL throughout the bus operation. Asynchronous Page Read. Asynchronous Page Read operations are used to read from several addresses within the same memory page. Each memory page is 4 Double-Words and is addressed by the address inputs A0 and A1. Data is read internally and stored in the Page Buffer. Valid bus operations are the same as Asynchronous Bus Read operations but with different timings. The first read operation within the page has identical timings, subsequent reads within the same page have much shorter access times. If the page changes then the normal, longer timings apply again. Page Read does not support Latched Controlled Read. See Figure 11, Asynchronous Page Read AC Waveforms and Table 18, Asynchronous Page Read AC Characteristics for details on when the outputs become valid. Asynchronous Bus Write. Asynchronous Bus Write operations write to the Command Interface in order to send commands to the memory or to latch addresses and input data to program. Bus Write operations are asynchronous, the clock, K, is don't care during Bus Write operations. A valid Asynchronous Bus Write operation begins by setting the desired address on the Address Inputs, and setting Chip Enable, Write Enable and Latch Enable Low, V IL, and Output Enable High, VIH, or Output Disable Low, V IL. The Address Inputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Commands and Input Data are latched on the rising edge of Chip Enable, E, or Write Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable Low, during the whole Asynchronous Bus Write operation. See Figure 12, Asynchronous Write AC Waveforms, and Table 19, Asynchronous Write and Latch Controlled Write AC Characteristics, for details of the timing requirements. Asynchronous Latch Controlled Bus Write. Asynchronous Latch Controlled Bus Write operations write to the Command Interface in order to send commands to the memory or to latch addresses and input data to program. Bus Write operations are asynchronous, the clock, K, is don't care during Bus Write operations. A valid Asynchronous Latch Controlled Bus Write operation begins by setting the desired address on
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the Address Inputs and pulsing Latch Enable Low, VIL. The Address Inputs are latched by the Command Interface on the rising edge of Latch Enable, Write Enable or Chip Enable, whichever occurs first. Commands and Input Data are latched on the rising edge of Chip Enable, E, or Write Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable Low, during the whole Asynchronous Bus Write operation. See Figure 13, Asynchronous Latch Controlled Write AC Waveforms, and Table 19, Asynchronous Write and Latch Controlled Write AC Characteristics, for details of the timing requirements. Output Disable. The data outputs are high impedance when the Output Enable, G, is at VIH or Output Disable, GD, is at VIL. Standby. When Chip Enable is High, VIH, and the Program/Erase Controller is idle, the memory enters Standby mode, the power consumption is reduced to the standby level and the Data Inputs/ Outputs pins are placed in the high impedance state regardless of Output Enable, Write Enable or Output Disable inputs. Automatic Low Power. If there is no change in the state of the bus for a short period of time during Asynchronous Bus Read operations the memory Table 4. Asynchronous Bus Operations
Bus Operation Asynchronous Bus Read Asynchronous Latch Controlled Bus Read Asynchronous Page Read Asynchronous Bus Write Asynchronous Latch Controlled Bus Write Output Disable, G Output Disable, GD Standby Reset/Power-Down
Note: X = Don't Care
enters Auto Low Power mode where the internal Supply Current is reduced to the Auto-Standby Supply Current. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Automatic Low Power is only available in Asynchronous Read modes. Power-Down. The memory is in Power-down when Reset/Power-Down, RP, is at V IL. The power consumption is reduced to the power-down level and the outputs are high impedance, independent of the Chip Enable, E, Output Enable, G, Output Disable, GD, or Write Enable, W, inputs. Electronic Signature. Two codes identifying the manufacturer and the device can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of the memory. The Electronic Signature is output by giving the Read Electronic Signature command. The manufacturer code is output when all the Address inputs are at VIL. The device code is output when A1 is at VIH and all the other address pins are at V IL. See Table 5. Issue a Read Memory Array command to return to Read mode.
Step
E VIL
G VIL VIH VIL VIL VIH VIL VIH VIH VIL X X
GD VIH VIH VIH VIH X VIH X VIH VIL X X
W VIH VIL VIH VIH VIL VIH VIL VIH VIH X X
RP VIH VIH VIH VIH VIH VIH VIH VIH VIH VIH VIL
L VIL VIL VIH X VIL VIL VIH X X X X
A0-A18 Address Address X Address Address Address X X X X X
DQ0-DQ31 Data Output High Z Data Output Data Output Data Input High Z Data Input High Z High Z High Z High Z
Address Latch Read
VIL VIL VIL VIL
Address Latch Write
VIL VIL VIL VIL VIH X
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Table 5. Asynchronous Read Electronic Signature Operation
Code Manufacturer Device M58BW016xB(1) Burst Configuration Register
Note: 1. x= B or D version of the device. 2. BCR= Burst Configuration Register.
Device All M58BW016xT(1)
E VIL VIL VIL VIL
G VIL VIL VIL VIL
GD VIH VIH VIH VIH
W VIH VIH VIH VIH
A18-A0 00000h 00001h 00001h 00005h
DQ31-DQ0 00000020h 00008836h 00008835h BCR (2)
Synchronous Bus Operations For synchronous bus operations refer to Table 6 together with the following text. Synchronous Burst Read. Synchronous Burst Read operations are used to read from the memory at specific times synchronized to an external reference clock. The burst type, length and latency can be configured. The different configurations for Synchronous Burst Read operations are described in the Burst Configuration Register section. Refer to Figures 5 and 6 for examples of synchronous burst operations. In continuous burst read, one burst read operation can access the entire memory sequentially by keeping the Burst Address Advance B at VIL for the appropriate number of clock cycles. At the end of the memory address space the burst read restarts from the beginning at address 000000h. A valid Synchronous Burst Read operation begins when the Burst Clock is active and Chip Enable and Latch Enable are Low, VIL. The burst start address is latched and loaded into the internal Burst Address Counter on the valid Burst Clock K edge (rising or falling depending on the value of M6) or on the rising edge of Latch Enable, whichever occurs first. After an initial memory latency time, the memory outputs data each clock cycle (or two clock cycles depending on the value of M9). The Burst Address Advance B input controls the memory burst output. The second burst output is on the next clock valid edge after the Burst Address Advance B has been pulled Low. Valid Data Ready, R, monitors if the memory burst boundary is exceeded and the Burst Controller of the microprocessor needs to insert wait states.
When Valid Data Ready is Low on the active clock edge, no new data is available and the memory does not increment the internal address counter at the active clock edge even if Burst Address Advance, B, is Low. Valid Data Ready may be configured (by bit M8 of Burst Configuration Register) to be valid immediately at the valid clock edge or one data cycle before the valid clock edge. Synchronous Burst Read will be suspended if Burst Address Advance, B, goes High, VIH. If Output Enable is at VIL and Output Disable is at VIH, the last data is still valid. If Output Enable, G, is at VIH or Output Disable, GD, is at VIL, but the Burst Address Advance, B, is at VIL the internal Burst Address Counter is incremented at each Burst Clock K valid edge. The Synchronous Burst Read timing diagrams and AC Characteristics are described in the AC and DC Parameters section. See Figures 14, 15, 16 and 17, and Table 20. Synchronous Burst Read Suspend. During a Synchronous Burst Read operation it is possible to suspend the operation, freeing the data bus for other higher priority devices. A valid Synchronous Burst Read operation is suspended when both Output Enable and Burst Address Advance are High, VIH. The Burst Address Advance going High, VIH, stops the burst counter and the Output Enable going High, V IH, inhibits the data outputs. The Synchronous Burst Read operation can be resumed by setting Output Enable Low.
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Table 6. Synchronous Burst Read Bus Operations
Bus Operation Step Address Latch Read Synchronous Burst Read Read Suspend Read Resume Burst Address Advance Read Abort, E Read Abort, RP E VIL VIL VIL VIL VIL VIH X G VIH VIL VIH VIL VIH X X GD X VIH X VIH X X X RP VIH VIH VIH VIH VIH VIH VIL K(3) T T X T T X X L VIL VIH VIH VIH VIH X X B X VIL VIH VIL VIL X X A0-A18 DQ0-DQ31 Address Input Data Output High Z Data Output High Z High Z High Z
Note: 1. X = Don't Care, VIL or VIH. 2. M15 = 0, Bit M15 is in the Burst Configuration Register. 3. T = transition, see M6 in the Burst Configuration Register for details on the active edge of K.
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Burst Configuration Register The Burst Configuration Register is used to configure the type of bus access that the memory will perform. The Burst Configuration Register is set through the Command Interface and will retain its information until it is re-configured, the device is reset, or the device goes into Reset/Power-Down mode. The Burst Configuration Register bits are described in Table 7. They specify the selection of the burst length, burst type, burst X and Y latencies and the Read operation. Refer to Figures 5 and 6 for examples of synchronous burst configurations. Read Select Bit (M15). The Read Select bit, M15, is used to switch between asynchronous and synchronous Bus Read operations. When the Read Select bit is set to '1', Bus Read operations are asynchronous; when the Read Select but is set to '0', Bus Read operations are synchronous. On reset or power-up the Read Select bit is set to'1' for asynchronous accesses. X-Latency Bits (M14-M11). The X-Latency bits are used during Synchronous Bus Read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Table 7, Burst Configuration Register. The X-Latency bits should also be selected in conjunction with Table , Burst Performance to ensure valid settings. Y-Latency Bit (M9). The Y-Latency bit is used during Synchronous Bus Read operations to set the number of clock cycles between consecutive reads. The Y-Latency value depends on both the X-Latency value and the setting in M9. When the Y-Latency is 1 the data changes each clock cycle; when the Y-Latency is 2 the data changes every second clock cycle. See Table 7, Burst Configuration Register and Table , Burst Performance, for valid combinations of the Y-Latency, the X-Latency and the Clock frequency. Valid Data Ready Bit (M8). The Valid Data Ready bit controls the timing of the Valid Data Ready output pin, R. When the Valid Data Ready bit is '0' the Valid Data Ready output pin is driven Low for the active clock edge when invalid data is output on the bus. When the Valid Data Ready bit is '1' the Valid Data Ready output pin is driven Low one clock cycle prior to invalid data being output on the bus. Burst Type Bit (M7). The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is '0' the memory outputs from interleaved addresses; when the Burst Type bit is '1' the memory outputs from sequential addresses. See Tables 8, Burst Type Definition, for the sequence of addresses output from a given starting address in each mode. Valid Clock Edge Bit (M6). The Valid Clock Edge bit, M6, is used to configure the active edge of the Clock, K, during Synchronous Burst Read operations. When the Valid Clock Edge bit is '0' the falling edge of the Clock is the active edge; when the Valid Clock Edge bit is '1' the rising edge of the Clock is active. Wrap Burst Bit (M3). The burst reads can be confined inside the 4 or 8 Double-Word boundary (wrap) or overcome the boundary (no wrap). The Wrap Burst bit is used to select between wrap and no wrap. When the Wrap Burst bit is set to `0' the burst read wraps; when it is set to `1' the burst read does not wrap. Burst Length Bit (M2-M0). The Burst Length bits set the maximum number of Double-Words that can be output during a Synchronous Burst Read operation before the address wraps. Burst lengths of 4 or 8 are available for both the Sequential and Interleaved burst types, and a continuous burst is available for the Sequential type. Table 7, Burst Configuration Register gives the valid combinations of the Burst Length bits that the memory accepts; Table 8, Burst Type Definition, gives the sequence of addresses output from a given starting address for each length. If either a Continuous or a No Wrap Burst Read has been initiated the device will output data synchronously. Depending on the starting address, the device activates the Valid Data Ready output to indicate that a delay is necessary before the data is output. If the starting address is aligned to an 8 Double Word boundary, the continuous burst mode will run without activating the Valid Data Ready output. If the starting address is not aligned to an 8 Double Word boundary, Valid Data Ready is activated to indicate that the device needs an internal delay to read the successive words in the array. M10, M5 and M4 are reserved for future use.
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Table 7. Burst Configuration Register
Bit M15 M14 001 010 M13-M11 X-Latency (2) 011 100 101 110 M10 M9 Y-Latency (3) 0 1 0 M8 Valid Data Ready 1 0 M7 Burst Type 1 0 M6 M5-M4 0 M3 Wrapping 1 001 M2-M0 Burst Length 010 111 No wrap 4 Double-Words 8 Double-Words Continuous Valid Clock Edge 1 Rising Burst Clock edge Reserved Wrap Sequential Falling Burst Clock edge R valid Low one data cycle before valid Burst Clock edge Interleaved Description 0 Read Select 1 Asynchronous Read (Default at power-on) Reserved Reserved 4, 4-1-1-1 (1) 5, 5-1-1-1, 5-2-2-2 6, 6-1-1-1, 6-2-2-2 7, 7-1-1-1, 7-2-2-2 8, 8-1-1-1, 8-2-2-2 Reserved One Burst Clock cycle Two Burst Clock cycles R valid Low during valid Burst Clock edge Value Synchronous Burst Read Description
Note: 1. 4 - 2 - 2 - 2 is not allowed. 2. X latencies can be calculated as: (t AVQV - tLLKH + tQVKH) + tSYSTEM MARGIN < (X -1) tK. (X is an integer number from 4 to 8 and tK is the clock period). 3. Y latencies can be calculated as: tKHQV + tSYSTEM MARGIN + tQVKH < Y tK. 4. tSYSTEM MARGIN is the time margin required for the calculation.
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Table 8. Burst Type Definition
M3 0 0 0 0 0 0 0 0 0 1 1 1 1 1 Starting Address 0 1 2 3 4 5 6 7 8 0 1 2 3 4 x4 Sequential 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 - - - - - 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 4-5-6-7 x4 Interleaved 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 - - - - - - - - - - x8 Sequential 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 - 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-1011 5-6-7-8-9-10-1112 6-7-8-9-10-1112-13 7-8-9-10-11-1213-14 8-9-10-11-12-1314-15 x8 Interleaved 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 - - - - - - Continuous 0-1-2-3-4-5-6-7-8-9-10.. 1-2-3-4-5-6-7-8-9-10-11.. 2-3-4-5-6-7-8-9-10-11-12.. 3-4-5-6-7-8-9-10-11-12-13.. 4-5-6-7-8-9-10-11-2-13-14.. 5-6-7-8-9-10-11-12-13-14.. 6-7-8-9-10-11-12-13-14-15.. 7-8-9-10-11-12-13-14-15-16.. 8-9-10-11-12-13-14-15-16-17.. 0-1-2-3-4-5-6-7-8-9-10.. 1-2-3-4-5-6-7-8-9-10-11.. 2-3-4-5-6-7-8-9-10-11-12.. 3-4-5-6-7-8-9-10-11-12-13.. 4-5-6-7-8-9-10-11-12-13-14..
1
5
5-6-7-8
-
-
5-6-7-8-9-10-11-12-13-14..
1
6
6-7-8-9
-
-
6-7-8-9-10-11-12-13-14-15..
1
7
7-8-9-10
-
-
7-8-9-10-11-12-13-14-15-16..
1
8
8-9-10-11
-
-
8-9-10-11-12-13-14-15-16-17..
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Figure 5. Example Burst Configuration X-1-1-1
0 K 1 2 3 4 5 6 7 8 9
ADD
VALID
L
DQ
4-1-1-1
VALID
VALID
VALID
VALID
VALID
VALID
DQ
5-1-1-1
VALID
VALID
VALID
VALID
VALID
DQ DQ DQ
6-1-1-1
VALID
VALID VALID
VALID
VALID VALID VALID
7-1-1-1
VALID VALID
8-1-1-1
AI03841
Figure 6. Example Burst Configuration X-2-2-2
0 K 1 2 3 4 5 6 7 8 9
ADD
VALID
L
DQ
NV
5-2-2-2
VALID
NV
VALID
NV
VALID
DQ DQ DQ
6-2-2-2
NV
VALID NV
NV
VALID NV
NV VALID NV
7-2-2-2
VALID NV
8-2-2-2
VALID
NV=NOT VALID
AI04406b
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COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. The Commands are summarized in Table 9, Commands. Refer to Table 9 in conjunction with the text descriptions below. Read Memory Array Command The Read Memory Array command returns the memory to Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent read operations will output the addressed memory array data. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus Read commands will access the memory array. Read Electronic Signature Command The Read Electronic Signature command is used to read the Manufacturer Code, the Device Code or the Burst Configuration Register. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is issued subsequent Bus Read operations, depending on the address specified, read the Manufacturer Code, the Device Code or the Burst Configuration Register until another command is issued; see Table 5, Read Electronic Signature. Read Query Command. The Read Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations, depending on the address specified, read from the Common Flash Interface Memory Area. See Appendix A, Tables 26, 27, 28, 29 and 30 for details on the information contained in the Common Flash Interface (CFI) memory area. Read Status Register Command The Read Status Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued subsequent Bus Read operations read the Status Register until another command is issued. The Status Register information is present on the output data bus (DQ1-DQ7) when Chip Enable E and Output Enable G are at V IL and Output Disable is at VIH. An interactive update of the Status Register bits is possible by toggling Output Enable or Output Disable. It is also possible during a Program or Erase operation, by disactivating the device with Chip Enable at V IH and then reactivating it with Chip En-
able and Output Enable at VIL and Output Disable at VIH. The content of the Status Register may also be read at the completion of a Program, Erase or Suspend operation. During a Block Erase, Program, Tuning Protection Program or Tuning Protection Unlock command, DQ7 indicates the Program/Erase Controller status. It is valid until the operation is completed or suspended. See the section on the Status Register and Table 11 for details on the definitions of the Status Register bits Clear Status Register Command The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to `0'. One Bus Write is required to issue the Clear Status Register command. Once the command is issued the memory returns to its previous mode, subsequent Bus Read operations continue to output the same data. The bits in the Status Register are sticky and do not automatically return to `0' when a new Program, Erase, Block Protect or Block Unprotect command is issued. If any error occurs then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program, Erase or Resume command. Block Erase Command The Block Erase command can be used to erase a block. It sets all of the bits in the block to `1'. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write operations are required to issue the command; the first write cycle sets up the Block Erase command, the second write cycle confirms the Block erase command and latches the block address in the internal state machine and starts the Program/Erase Controller. The sequence is aborted if the Confirm command is not given and the device will output the Status Register Data with bits 4 and 5 set to '1'. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Erase operation the memory will only accept the Read Status Register command and the Program/ Erase Suspend command. All other commands will be ignored. Typical Erase times are given in Table 10.
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See Appendix B, Figure 23, Block Erase Flowchart and Pseudo Code, for a suggested flowchart on using the Block Erase command. Program Command. The Program command is used to program the memory array. Two Bus Write operations are required to issue the command; the first write cycle sets up the Program command, the second write cycle latches the address and data to be programmed in the internal state machine and starts the Program/Erase Controller. A program operation can be aborted by writing FFFFFFFFh to any address after the program set-up command has been given. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Program operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. The program operation aborts if VPP drops out of the allowed ranges or if Reset/Power-down RP falls to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory block must be erased and reprogrammed. See Appendix B, Figure 21, Program Flowchart and Pseudo Code, for a suggested flowchart on using the Program command. Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Erase operation. The command will only be accepted during a Program or Erase operation. It can be issued at any time during a program or erase operation. The command is ignored if the device is already in suspend mode. One Bus Write cycle is required to issue the Program/Erase Suspend command and pause the Program/Erase Controller. Once the command is issued it is necessary to poll the Program/Erase Controller Status bit (bit 7) to find out when the Program/Erase Controller has paused; no other commands will be accepted until the Program/ Erase Controller has paused. After the Program/ Erase Controller has paused, the memory will continue to output the Status Register until another command is issued. During the polling period between issuing the Program/Erase Suspend command and the Program/ Erase Controller pausing it is possible for the operation to complete. Once the Program/Erase Controller Status bit (bit 7) indicates that the Program/Erase Controller is no longer active, the Program Suspend Status bit (bit 2) or the Erase Suspend Status bit (bit 6) can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing see Table 10. During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic Signature, Read Query and Program/Erase Resume commands will be accepted by the Command Interface. Additionally, if the suspended operation was Erase then the Program and the Program Suspend commands will also be accepted. When a program operation is completed inside a Block Erase Suspend the Read Memory Array command must be issued to reset the device in Read mode, then the Erase Resume command can be issued to complete the whole sequence. Only the blocks not being erased may be read or programmed correctly. See Appendix B, Figure 22, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 24, Erase Suspend & Resume Flowchart and Pseudo Code, for suggested flowcharts on using the Program/Erase Suspend command. Program/Erase Resume Command The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the Program/Erase Resume command. See Appendix B, Figure 22, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 24, Erase Suspend & Resume Flowchart and Pseudo Code, for suggested flowcharts on using the Program/Erase Resume command. Set Burst Configuration Register Command. The Set Burst Configuration Register command is used to write a new value to the Burst Configuration Control Register which defines the burst length, type, X and Y latencies, Synchronous/ Asynchronous Read mode and the valid Clock edge configuration. Two Bus Write cycles are required to issue the Set Burst Configuration Register command. The first cycle writes the setup command and the address corresponding to the Set Burst Configuration Register content. The second cycle writes the Burst Configuration Register data and the confirm command. Once the command is issued the memory returns to Read mode as if a Read Memory Array command had been issued. The value for the Burst Configuration Register is always presented on A0-A15. M0 is on A0, M1 on A1, etc.; the other address bits are ignored. Tuning Protection Unlock Command The Tuning Protection Unlock command unlocks the tuning protected blocks by writing the 64bit
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Tuning Protection Code (M58BW016B only). After a reset or power-up the blocks are locked and so a Tuning Protection Unlock command must be issued to allow program or erase operations on tuning protected block or to program a new Tuning Protection Code. Read operations output the Status Register content after the unlock operation has started. The Tuning Protection Code is composed of 64 bits, but the data bus is 32 bits wide so four (2 x 2) write cycles are required to unlock the device. s The first write cycle issues the Tuning Protection Unlock Setup command (0x78).
s
The second write cycle inputs the first 32 bits of the tuning protection code on the data bus, at address 0x00000.
Bit 7 of the Status Register should now be checked to verify that the device has successfully stored the first part of the code in the internal register. If b7 = `1', the device is ready to accept the second part of the code. This does not mean that the first 32 bits match the tuning protection code, simply that it was correctly stored for the comparing. If b7 = `0', the user must wait for this bit setting (refer to write cycle AC timings). s The third write cycle re-issues the Tuning Protection Unlock Setup command (0x78).
s
form the Tuning Protection Program sequence. The device can be re-locked with a reset or powerdown. See Appendix B, Figure 25, 26 and 27 for suggested flowcharts for using the Tuning Protection Unlock command. Tuning Protection Program Command. The Tuning Protection Program command is used to program a new Tuning Protection Code which can be configured by the designer of the application (M58BW016B only). The device should be unlocked by the Tuning Protection Unlock command before issuing the Tuning Protection Program command. Read operations output the Status Register content after the program operation has started. The Tuning Protection Code is composed of 64 bits, but the data bus is 32 bits wide so four (2 x 2) write cycles are required to program the code. s The first write cycle issues the Tuning Protection Program Setup command (0x48).
s
The second write cycle inputs the first 32 bits of the new tuning protection code on the data bus, at address 0x00000.
The fourth write cycle inputs the second 32 bits of the code at address 0x00001.
Bit 7 of the Status Register should again be checked to verify that the device has successfully stored the second part of the code. When the device is ready (b7 = `1'), the tuning protection status can be monitored on Status Register bit0. If b0 = `0' the device is locked; b0 = `1' the device is unlocked. If the device is still locked a Read Memory Array command must be issued before re-issuing the Tuning Protection Unlock command. Device locked means that the 64 bit password is wrong. If the unlock operation is attempted using a wrong code on an already unlocked device, the device becomes locked. Status register bit 4 is set to '1' if there has been a verify failure. Unlocking aborts if VPP drops out of the allowed range or RP goes to VIL. Once the device is successfully unlocked, a Read Memory Array command must be issued to return the memory to read mode before issuing any other commands. The user can then program or erase all blocks, depending on WP status and VPP level. At this point, it is also possible to configure a new protection code. To write a new protection code into the device tuning register, the user must per-
Bit 7 of the Status Register should now be checked to verify that the device has successfully stored the first part of the code in the internal register. If b7 = `1', the device is ready to accept the second part of the code. If b7 = `0', the user must wait for this bit setting (refer to write cycle AC timings). s The third write cycle re-issues the Tuning Protection Program Setup command (0x48).
s
The fourth write cycle inputs the second 32 bits of the new code at address 0x00001.
Bit 7 of the Status Register should again be checked to verify that the device has successfully stored the second part of the code. When the device is ready (b7 = `1'). After completion Status Register bit 4 is set to '1' if there has been a program failure. Programming aborts if VPP drops out of the allowed range or RP goes to V IL. A Read Memory Array command must be issued to return the memory to read mode before issuing any other commands. Once the code has been changed a device reset or power-down will make the protection active with the new code. See Appendix B, Figure 25, 26 and 27 for suggested flowcharts for using the Tuning Protection Program command.
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Table 9. Commands
Command Cycles Bus Operations 1st Cycle Op. Addr. X X X Data FFh 90h 90h Op. Read 2nd Cycle Addr. RA Data RD 20h IDh 3rd Cycle Op. Addr. Data Op. 4th Cycle Addr. Data
Read Memory Array Read Electronic Signature (Manufacturer Code) Read Electronic Signature (Device Code) Read Electronic Signature (Burst Configuration Register) Read Status Register Read Query Clear Status Register Block Erase Program Program/Erase Suspend Program/Erase Resume Set Burst Configuration Register Tuning Protection(2) Program Tuning Protection Unlock(2)
2 Write 2 Write 2 Write 2 Write 2 Write
Read 00000h Read 00001h
X X X X X X X X X X X
90h 70h 98h 50h 20h 40h 10h B0h D0h 60h 48h 78h
Read 00005h BCRh Read Read X QAh SRDh QDh
2 Write 1 2 2 1 1 2 4 4 Write Write Write Write Write Write Write Write
Write Write
BAh PA
D0h PD
Write Write Write
BCRh TPAh TPAh
03h TPCh Write TPCh Write X X 48h Write TPAh TPCh 78h Write TPAh TPCh
Note: 1. X Don't Care; RA Read Address, RD Read Data, ID Device Code, SRD Status Register Data, PA Program Address; PD Program Data, QA Query Address, QD Query Data, BA Any address in the Block, BCR Burst Configuration Register value, TPA = Tuning Protection Address, TPC = Tuning Protection Code. 2. Cycles 1 and 2 input the first 32 bits of the code, cycles 3 and 4 the second 32 bits of the code.
Table 10. Program, Erase Times and Program Erase Endurance Cycles
M58BW016B/D Parameters Min Typ VPP = VDD Parameter Block (64Kb) Program Main Block (512Kb) Program Parameter Block Erase Main Block Erase Program Suspend Latency Time Erase Suspend Latency Time Program/Erase Cycles (per Block) 100,000 0.030 0.23 0.8 1.5 3 10 VPP = 12V 0.016 0.13 0.64 0.9 Max VPP = VDD 0.060 0.46 1.8 3 10 30 VPP = 12V 0.032 0.26 1.5 1.8 s s s s s s cycles Unit
Note: TA = -40 to 125C, VDD = 2.7V to 3.6V, VDDQ = 2.4V to VDD
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M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
STATUS REGISTER The Status Register provides information on the current or previous Program, Erase, Block Protect or Tuning Protection operation. The various bits in the Status Register convey information and errors on the operation. They are output on DQ7-DQ0. To read the Status Register the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase, Block Protect, Program/Erase Resume commands. The Status Register can be read from any address. The contents of the Status Register can be updated during an erase or program operation by toggling the Output Enable or Output Disable pins or by dis-activating (Chip Enable, VIH) and then reactivating (Chip Enable and Output Enable, VIL, and Output Disable, V IH.) the device. The Status Register bits are summarized in Table 11, Status Register Bits. Refer to Table 11 in conjunction with the following text descriptions. Program/Erase Controller Status (Bit 7) The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is set to `0', the Program/Erase Controller is active; when bit7 is set to `1', the Program/Erase Controller is inactive. The Program/Erase Controller Status is set to `0' immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is set to `1'. During Program and Erase operations the Program/Erase Controller Status bit can be polled to find the end of the operation. The other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is set to `1'. After the Program/Erase Controller completes its operation the Erase Status (bit5), Program Status and Tuning Protection Unlock status (bit4) bits should be tested for errors. Erase Suspend Status (Bit 6) The Erase Suspend Status bit indicates that an Erase operation has been suspended and is waiting to be resumed. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is set to `1' (Program/Erase Controller inactive); after a Program/ Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Erase Suspend Status bit is set to `0', the Program/Erase Controller is active or has completed its operation; when the bit is set to `1', a Program/Erase Suspend command has been issued
and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns to `0'. Erase Status (Bit 5) The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Erase Status bit is set to `0', the memory has successfully verified that the block has erased correctly. When the Erase Status bit is set to `1', the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. Once set to `1', the Erase Status bit can only be reset to `0' by a Clear Status Register command or a hardware reset. If set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status, Tuning Protection Unlock Status (Bit 4) The Program Status and Tuning Protection Unlock Status bit is used to identify a Program failure or a Tuning Protection Code verify failure. Bit4 should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When bit4 is set to `0' the memory has successfully verified that the device has programmed correctly or that the correct Tuning Protection Code has been written. When bit4 is set to `1' the device has failed to verify that the data has been programmed correctly or that the correct Tuning Protection code has been written. Once set to 1', the Program Status bit can only be reset to `0' by a Clear Status Register command or a hardware reset. If set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. VPP Status (Bit 3) The VPP Status bit can be used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if V PP becomes invalid during an operation. When the VPP Status bit is set to `0', the voltage on the VPP pin was sampled at a valid voltage; when the VPP Status bit is set to `1', the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK, the memory is protected; Program Erase, operations cannot be performed. Once set to `1', the VPP Status bit can only be reset to `0' by a Clear Status Register command or a
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hardware reset. If set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Suspend Status (Bit 2) The Program Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is set to `1' (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Program Suspend Status bit is set to `0', the Program/Erase Controller is active or has completed its operation; when the bit is set to `1', a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Program Suspend Status bit returns to `0'. Block Protection Status (Bit 1) The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the contents of a protected block. Table 11. Status Register Bits
Bit 7 Program/Erase Controller Status '0' 6 Erase Suspend Status '0' 5 Erase Status '0' 4 Program Status, Tuning Protection Unlock Status V PP Status '0' 2 Program Suspend Status '0' 1 Erase/Program in a Protected Block 0 Tuning Protection Status '0'
Note: 1. For the M58BW016D version the Tuning Protection Status bit is always set to `1'.
When the Block Protection Status bit is set to `0', no Program or Erase operations have been attempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is set to `1', a Program or Erase operation has been attempted on a protected block. Once set to `1', the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Tuning Protection Status (Bit 0) The Tuning Protection Status bit indicates if the device is locked (Tuning Protection is enabled) or unlocked (Tuning Protection is disabled). When the Tuning Protection Status bit is set to `0' the device is locked, when it is set to `1' the device is unlocked. After a reset or power-up the device is locked and so bit0 is set to `0'. The Tuning Protection Status bit is set to `1' for the M58BW016D version.
Name
Logic Level '1' Ready Busy Suspended
Definition
'1'
In Progress or Completed Erase Error Erase Success Program Error Program Success VPP Invalid, Abort VPP OK Suspended In Progress or Completed Program/Erase on Protected Block, Abort No Operations to Protected Sectors Tuning Protection Disabled(1) Tuning Protection Enabled
'1'
'1' '0' '1'
3
'1'
'1' '0' '1'
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MAXIMUM RATING Stressing the device above the ratings listed in Table 12, Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 12. Absolute Maximum Ratings
Value Symbol TBIAS TSTG VIO VDD, VDDQ, VDDQIN VPP Parameter Min Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Program Voltage -40 -55 -0.6 -0.6 -0.6 Max 125 155 VDDQ +0.6 VDDQIN +0.6 4.2 13.5 (1) C C V V V Unit
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: Cumulative time at a high voltage level of 13.5V should not exceed 80 hours on VPP pin.
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DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measure-
ment Conditions summarized in Table 13, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 13. Operating and AC Measurement Conditions
Value Parameter Min Supply Voltage (VDD) Input/Output Supply Voltage (VDDQ) Grade 6 Ambient Temperature (TA) Grade 3 Load Capacitance (CL) Clock Rise and Fall Times Input Rise and Fall Times Input Pulses Voltages Input and Output Timing Ref. Voltages 0 to VDDQ VDDQ/2 -40 60 4 4 125 C pF ns ns V V 2.7 2.4 -40 Max 3.6 VDD 90 V V C Units
Figure 7. AC Measurement Input Output Waveform
VDDQ VDDQIN
Figure 8. AC Measurement Load Circuit
1.3V
1N914 VDDQ/2 VDDQIN/2 3.3k
AI04153
0V
Note: VDD = VDDQ.
DEVICE UNDER TEST CL
OUT
CL includes JIG capacitance
AI04154
Table 14. Device Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Typ 6 8 Max 8 12 Unit pF pF
Note: 1. TA = 25C, f = 1 MHz 2. Sampled only, not 100% tested.
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Table 15. DC Characteristics
Symbol ILI ILO IDD IDDB Parameter Input Leakage Current Output Leakage Current Supply Current (Random Read) Supply Current (Burst Read) Supply Current (Standby) IDD1 Supply Current (Auto Low-Power) IDD2 IDD3 IDD4 IPP IPP1 IPP2 IPP3 Supply Current (Reset/Power-down) Supply Current (Program or Erase, Set Lock Bit, Erase Lock Bit) Supply Current (Erase/Program Suspend) Program Current (Read or Standby) Program Current (Read or Standby) Program Current (Power-down) Program Current (Program) Program in Progress Test Condition 0V VIN VDDQ 0V VOUT VDDQ E = VIL, G = VIH, fadd = 6MHz E = VIL, G = VIH, fclock = 56MHz E = RP = VDD 0.2V E = VSS 0.2V, RP = VDD 0.2V RP = VSS 0.2V Program, Block Erase in progress E = VIH VPP VPP1 VPP VPP1 RP = VIL VPP = VPP1 VPP = VPPH Program Current (Erase) Erase in Progress Input Low Voltage Input High Voltage (for DQ lines) Input High Voltage (for Input only lines) Output Low Voltage Output High Voltage CMOS Program Voltage (Program or Erase operations) Program Voltage (Program or Erase operations) VDD Supply Voltage (Erase and Program lockout) IOL = 100A IOH = -100A VDDQ -0.1 2.7 11.4 3.6 12.6 2.2 VPP = VPP1 VPP = VPPH -0.5 0.8VDDQIN 0.8VDDQIN Min Max 1 5 20 30 60 60 60 30 40 30 30 5 200 20 200 20 0.2VDDQIN VDDQ +0.3 3.6 0.1 Unit A A mA mA A A A mA A A A A A mA A mA V V V V V V V V
IPP4 VIL VIH VIH VOL VOH VPP1 VPPH VLKO
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Figure 9. Asynchronous Bus Read AC Waveforms
tAVAV tAVAV A0-A18 A0-A18 tAVQV tAVQV tLLEL tLLEL tEHLX tEHLX VALID VALID
LL
tELQX tELQX tELQV tELQV E E tGLQX tGLQX tGLQV tGLQV G G tEHQX tEHQX tEHQZ tEHQZ tAXQX tAXQX
GD GD tGHQX tGHQX tGHQZ tGHQZ DQ0-DQ31 DQ0-DQ31 OUTPUT OUTPUT See also Page Read See also Page Read
AI04407C
AI04407C
Table 16. Asynchronous Bus Read AC Characteristics.
M58BW016 Symbol tAVAV tAVQV tAXQX tEHLX tEHQX tEHQZ tELQV(1) tELQX tGHQX tGHQZ tGLQV tGLQX tLLEL Parameter Address Valid to Address Valid Address Valid to Output Valid Address Transition to Output Transition Chip Enable High to Latch Enable Transition Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable to Output Transition Latch Enable Low to Chip Enable Low G = VIL G = VIL G = VIL G = VIL E = VIL E = VIL E = VIL E = VIL Test Condition 80 E = VIL, G = VIL E = VIL, G = VIL E = VIL, G = VIL Min Max Min Min Min Max Max Min Min Max Max Min Min 80 80 0 0 0 20 80 0 0 15 25 0 0 90 90 90 0 0 0 20 90 0 0 15 25 0 0 100 100 100 0 0 0 20 100 0 0 15 25 0 0 ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Output Enable G may be delayed up to t ELQV - tGLQV after the falling edge of Chip Enable E without increasing tELQV.
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Figure 10. Asynchronous Latch Controlled Bus Read AC Waveforms
A0-A18 tAVLL
VALID tLHAX
L
tLHLL
tLLLH tELLL
tEHLX
E tGLQX tGLQV G tLLQX tLLQV DQ0-DQ31 OUTPUT See also Page Read
AI03645
tEHQX tEHQZ
tGHQX GHQZ
Table 17. Asynchronous Latch Controlled Bus Read AC Characteristics
M58BW016 Symbol tAVLL tEHLX tEHQX tEHQZ tELLL tGHQX tGHQZ tGLQV tGLQX tLHAX tLHLL tLLLH tLLQV tLLQX Parameter Address Valid to Latch Enable Low Chip Enable High to Latch Enable Transition Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Latch Enable Low Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Latch Enable High to Address Transition Latch Enable High to Latch Enable Low Latch Enable Low to Latch Enable High Latch Enable Low to Output Valid Latch Enable Low to Output Transition E = VIL E = VIL, G = VIL E = VIL, G = VIL E = VIL E = VIL E = VIL E = VIL E = VIL G = VIL G = VIL Test Condition 80 E = VIL Min Min Min Max Min Min Max Max Min Min Min Min Max Min 0 0 0 20 0 0 15 25 0 5 10 10 80 0 90 0 0 0 20 0 0 15 25 0 5 10 10 90 0 100 0 0 0 20 0 0 15 25 0 5 10 10 100 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
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Figure 11. Asynchronous Page Read AC Waveforms
A0-A1
A0 and/or A1 tAVQV1 tAXQX
DQ0-DQ31
OUTPUT
OUTPUT + 1
AI03646
Table 18. Asynchronous Page Read AC Characteristics
M58BW016 Symbol tAVQV1 tAXQX Parameter Address Valid to Output Valid Address Transition to Output Transition Test Condition 80 E = VIL, G = VIL E = VIL, G = VIL Max Min 25 6 90 25 6 100 25 6 ns ns Unit
Note: For other timings see Table 16, Asynchronous Bus Read Characteristics.
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A0-A18 VALID tWHAX VALID VALID
tAVWH
E=L tWHEH
tAVLL
G tELWL tWLWH tWHGL tWHWL
Figure 12. Asynchronous Write AC Waveform
W tDVWH INPUT tWHDX INPUT tWHQV VALID SR
DQ0-DQ31
tVPHWH
tQVVPL
VPP tPHWH RP = VHH tQVPL RP = VDD
RP
Write Cycle
Write Cycle
Read Status Register
M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
AI03651
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VALID tLHAX VALID VALID tWHAX tLLWH tELLL tAVWH tWHEH tWHWL tWHGL tWLWH tDVWH INPUT tWHDX tVPHWH INPUT tWHQV VALID SR tQVVPL tQVPL RP = VHH RP = VDD Write Cycle Write Cycle Read Status Register
AI03652
A0-A18
tAVLH
L
tLLLH
tAVLL
E
G
tELWL
W
Figure 13. Asynchronous Latch Controlled Write AC Waveform
M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
DQ0-DQ31
VPP
RP
M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics
M58BW016 Symbol tAVLL tAVWH tDVWH tELLL tELWL tLHAX tLLLH tLLWH tQVVPL tVPHWH tWHAX tWHDX tWHEH tWHGL tWHQV tWHWL tWLWH tQVPL Parameter Address Valid to Latch Enable Low Address Valid to Write Enable High Data Input Valid to Write Enable High Chip Enable Low to Latch Enable Low Chip Enable Low to Write Enable Low Latch Enable High to Address Transition Latch Enable Low to Latch Enable High latch Enable Low to Write Enable High Output Valid to VPP Low VPP High to Write Enable High Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Output Enable Low Write Enable High to Output Valid Write Enable High to Write Enable Low Write Enable Low to Write Enable High Output Valid to Reset/Power-down Low E = VIL E = VIL E = VIL E = VIL E = VIL E = VIL Test Condition 80 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 0 50 50 0 0 5 10 50 0 0 0 0 0 150 175 20 60 0 90 0 50 50 0 0 5 10 50 0 0 0 0 0 150 175 20 60 0 100 0 50 50 0 0 5 10 50 0 0 0 0 0 150 175 20 60 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
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0 1 n n+1 n+2 tKHAX VALID tKHLX tAVLL tELLL tAVQV tEHQX tEHQZ tGLQV tGHQX tGHQZ tKHQV tQVKH OUTPUT Setup
AI04409
K
tKHLL
A0-A18
tLLKH
L
E
M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
G
Figure 14. Synchronous Burst Read (Data Valid from 'n' Clock Rising Edge)
DQ0-DQ31
Note: n depends on Burst X-Latency.
M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
Table 20. Synchronous Burst Read AC Characteristics
M58BW016 Symbol tAVLL tBHKH tBLKH tELLL tGLQV tKHAX tKHLL tKHLX tKHQX tLLKH tQVKH(1) tRLKH tKHQV Parameter Address Valid to Latch Enable Low Burst Address Advance High to Valid Clock Edge Burst Address Advance Low to Valid Clock Edge Chip Enable Low to Latch Enable low Output Enable Low to Output Valid Valid Clock Edge to Address Transition Valid Clock Edge to Latch Enable Low Valid Clock Edge to Latch Enable Transition Valid Clock Edge to Output Transition Latch Enable Low to Valid Clock Edge Output Valid to Valid Clock Edge Valid Data Ready Low to Valid Clock Edge Valid Clock Edge to Output Valid E = VIL, L = VIH E = VIL E = VIL E = VIL E = VIL, G = VIL, L = VIH E = VIL E = VIL, G = VIL, L = VIH E = VIL, G = VIL, L = VIH E = VIL, G = VIL, L = VIH Test Condition 80 E = VIL E = VIL, G = VIL, L = VIH E = VIL, G = VIL, L = VIH Min Min Min Min Min Min Min Min Min Min Min Min Max 0 8 8 0 25 5 0 0 3 6 6 6 10 90 0 8 8 0 25 5 0 0 3 6 6 6 10 100 0 8 8 0 25 5 0 0 3 6 6 6 10 ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Data output should be read on the valid clock edge. 2. For other timings see Table 16, Asynchronous Bus Read Characteristics.
Figure 15. Synchronous Burst Read (Data Valid from 'n' Clock Rising Edge)
n K tKHQV tQVKH DQ0-DQ31 Q0
n+1
n+2
n+3
n+4
n+5
Q1 tKHQX
Q2
Q3
Q4
Q5
SETUP
Burst Read Q0 to Q3
Note: n depends on Burst X-Latency AI04408b
Note: For set up signals and timings see Synchronous Burst Read.
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Figure 16. Synchronous Burst Read - Continuous - Valid Data Ready Output
K
Output (1)
V
V
V tRLKH
V
V
R
(2)
AI03649
Note: Valid Data Ready = Valid Low during valid clock edge 1. V= Valid output. 2. R is an open drain output with an internal pull up resistor of 1M. The internal timing of R follows DQ. An external resistor, typically 300k. for a single memory on the R bus, should be used to give the data valid set up time required to recognize that valid data is available on the next valid clock edge.
Figure 17. Synchronous Burst Read - Burst Address Advance
K
ADD
VALID
L
ADD tGLQV G tBLKH B
Q0
Q1
Q2
tBHKH
AI03650
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Figure 18. Reset, Power-Down and Power-up AC Waveform
W, E, G
tPHWL tPHEL tPHGL
tPLRH
R tPHWL tPHEL tPHGL RP tVDHPH VDD, VDDQ Power-Up Reset
AI03849b
tPLPH
Table 21. Reset, Power-Down and Power-up AC Characteristics
Symbol tPHEL tPHQV (1) tPHWL tPHGL tPLPH tPLRH tVDHPH Parameter Reset/Power-down High to Chip Enable Low Reset/Power-down High to Output Valid Reset/Power-down High to Write Enable Low Reset/Power-down High to Output Enable Low Reset/Power-down Low to Reset/Power-down High Reset/Power-down Low to Valid Data Ready High Supply Voltages High to Reset/Power-down High 50 50 100 2 10 30 Min 50 130 Max Unit ns ns ns ns ns s s
Note: 1. This time is tPHEL + tAVQV or tPHEL + t ELQV.
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PACKAGE MECHANICAL Figure 19. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Bottom View Package Outline
D FD FE SD D1
SE E E1 BALL "A1" ddd
e e A A1 b A2
BGA-Z05
Note: Drawing is not to scale.
Table 22. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE 12.000 9.000 1.000 1.500 1.500 0.500 0.500 - - - - - - - 0.400 1.100 0.500 10.000 7.000 - - - - - - 0.150 - - - - - - - 0.4724 0.3543 0.0394 0.0591 0.0591 0.0197 0.0197 - - - - - - - 0.350 Min Max 1.700 0.450 0.0157 0.0433 0.0197 0.3937 0.2756 - - - - - - 0.0059 - - - - - - - 0.0138 Typ Min Max 0.0669 0.0177 inches
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Figure 20. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline
Ne A2
N 1
e Nd D2 D1 D b
E2 E1 E L1
A CP
c
QFP-B
A1
L
Note: Drawing is not to scale.
Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data
Symbol A A1 A2 b c D D1 D2 e E E1 E2 L L1 N Nd Ne 23.200 20.000 18.400 0.800 17.200 14.000 12.000 0.800 1.600 2.800 0.250 2.550 0.300 0.130 22.950 19.900 - - 16.950 13.900 - 0.650 - 0 80 24 16 3.050 0.450 0.230 23.450 20.100 - - 17.450 14.100 - 0.950 - 7 0.9134 0.7874 0.7244 0.0315 0.6772 0.5512 0.4724 0.0315 0.0630 0.1102 millimeters Typ Min Max 3.400 0.0098 0.1004 0.0118 0.0051 0.9035 0.7835 - - 0.6673 0.5472 - 0.0256 - 0 80 24 16 0.1201 0.0177 0.0091 0.9232 0.7913 - - 0.6870 0.5551 - 0.0374 - 7 Typ inches Min Max 0.1339
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PART NUMBERING Table 24. Ordering Information Scheme
Example: Device Type M58 Architecture B = Burst Mode Operating Voltage W = VDD = 2.7V to 3.6V; VDDQ = VDDQIN =2.4 to VDD Device Function 016B = 16 Mbit (x32), Boot Block, Burst Tuning Protection 016D = 16 Mbit (x32), Boot Block, Burst no Tuning Protection Array Matrix T = Top Boot B = Bottom Boot Speed 80 = 80ns 90 = 90ns 100 = 100ns Package T = PQFP80 ZA = LBGA80: 1.0mm pitch Temperature Range 3 = -40 to 125 C 6 = -40 to 85 C Option T = Tape & Reel Packing M58BW016B T 80 T 3 T
Note: Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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REVISION HISTORY Table 25. Document Revision History
Date January-2001 05-Jun-2001 15-Jun-2001 17-Jul-2001 Version -01 -02 -03 -04 First Issue. Major rewrite and restructure. Nd and Ne values changed in PQFP80 Package Mechanical Table PQFP80 Package Outline Drawing and Mechanical Data Table updated tLEAD removed from Absolute Maximum Ratings (Table 12) 80, 90 and 100ns Speed classes defined (Tables 16, 17, 18, 19 and 20 clarified accordingly) Figures 14, 15, 16 and 17 clarified Temperature range 3 and 6 added Tables 13, 14, 15, 21 and CFI Tables 27, 28, 29, 30 clarified Document status changed from Product Preview to Preliminary Data DC Characteristics IPP, IPP1 and IDD1 clarified AC Bus Read Characteristics timing tGHQZ clarified Revision numbering modified: a minor revision will be indicated by incrementing the tenths digit, and a major revision, by incrementing the units digit of the previous version (e.g. revision version 06 becomes 6.0). References of VPP pin used for block protection purposes removed. Figure 9 modified. Datasheet status changed from Preliminary Data to full Datasheet. tWLWH parameter modified in Table 19, Asynchronous Write and Latch Controlled Write AC Characteristics. Revision Details
17-Dec-2001
-05
17-Jan-2002
-06
30-Aug-2002
6.1
4-Sep-2002
7.0
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APPENDIX A. COMMON FLASH INTERFACE - CFI The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the deTable 26. Query Structure Overview
Offset 00h 01h 10h 1Bh 27h P(h)(1) A(h)(2) CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query Table Alternate Algorithm-specific Extended Query Table Sub-section Name Manufacturer Code Device Code Command set ID and algorithm data offset Device timing and voltage information Flash memory layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional) Description
vice, enabling the software to upgrade itself when necessary. When the CFI Query Command (RCFI) is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 26, 27, 28, 29 and 30 show the addresses used to retrieve the data.
Note: 1. Offset 15h defines P which points to the Primary Algorithm Extended Query Address Table. 2. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.
Table 27. CFI - Query Address and Data Output
Address A0-A18 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 51h 52h 59h 03h 00h 35h Primary algorithm extended Query Address Table: P(h) 00h 00h 00h 00h Alternate Algorithm Extended Query address Table 00h
Note: 1. The x8 or Byte Address and the x16 or Word Address mode are not available. 2. Query Data are always presented on DQ7-DQ0. DQ31-DQ8 are set to '0'.
Data "Q" "R" "Y" Query ASCII String
Instruction 51h; "Q" 52h; "R" 59h; "Y"
Primary Vendor: Command Set and Control Interface ID Code
Alternate Vendor: Command Set and Control Interface ID Code
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M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
Table 28. CFI - Device Voltage and Timing Specification
Address A0-A18 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 27h (1) 36h (1) B4h (2) C6h (2) 00h (3) 00h (3) 0Ah 00h (3) 00h (3) 00h 04h 00h (3) VDD min, 2.7V VDD max, 3.6V VPP min VPP max 2n ms typical time-out for Word, DWord prog - Not Available 2n ms, typical time-out for max buffer write - Not Available 2n ms, typical time-out for Erase Block 2n ms, typical time-out for chip erase - Not Available 2n x typical for Word Dword time-out max - Not Available 2n x typical for buffer write time-out max - Not Available 2n x typical for individual block erase time-out maximum 2n x typical for chip erase max time-out - Not Available Description
Note: 1. Bits are coded in Binary Code Decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV. 2. Bit7 to bit4 are coded in Hexadecimal and scaled in Volts while bit3 to bit0 are in Binary Code Decimal and scaled in 100mV. 3. Not supported.
Table 29. Device Geometry Definition
Address A0-A18 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h Data 15h 03h 00h 00h 00h 02h 1Eh Number (n-1) of blocks of identical size; n=31 00h 00h 01h 07h Number (n-1) of blocks of identical size; n=8 00h 20h 00h Erase Block region information x 256 bytes per Erase Block (8Kbytes) Erase Block region information x 256 bytes per Erase Block (64Kbytes) Description 2n number of bytes memory size Device Interface Sync./Async. Organization Sync./Async. Page size in bytes, 2n Bit7-0 = number of Erase Block Regions in device
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Table 30. Extended Query information
Address offset (P)h (P+1)h (P+2)h (P+3)h (P+4)h Address A18-A0 35h 36h 37h 38h 39h Data (Hex) 50h 52h 49h 31h 31h "P" "R" "Y" Major version number Minor version number Optional Feature: (1=yes, 0=no) bit0, Chip Erase Supported (0=no) bit1, Suspend Erase Supported (1=yes) bit2, Suspend Program Supported (1=yes) bit3, Lock/Unlock Supported (1=yes) bit4, Queue Erase Supported (0=no) Bit 31-5 reserved for future use Query ASCII string - Extended Table Description
(P+5)h
3Ah
86h
(P+6)h (P+7)h (P+8)h (P+9)h (P+A)h
3Bh 3Ch 3Dh 3Eh 3Fh
01h 00h 00h 01h 00h (1) Function allowed after Suspend: Program allowed after Erase Suspend (1=yes) Bit 7-1 reserved for future use Block Status Register Mask - Not Available Optional Features: Synchronous Read supported
Note: 1. Not supported.
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APPENDIX B. FLOW CHARTS Figure 21. Program Flowchart and Pseudo Code
Start
Write 40h
Write Address & Data
Program Command: - write 40h - write Address & Data (memory enters read status state after the Program command)
Read Status Register
do: - read status register (E or G must be toggled) NO
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
while b7 = 1
NO
VPP Invalid Error (1)
If b3 = 1, VPP invalid error: - error handler
NO
Program Error (1)
If b4 = 1, Program error: - error handler
NO
Program to Protect Block Error
If b1 = 1, Program to Protected Block Error: - error handler
AI03850
Note: 1. If an error is found, the Status Register must be cleared before further P/E operations.
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Figure 22. Program Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Write 70h
Program/Erase Suspend Command: - write B0h - write 70h do: - read status register
Read Status Register
b7 = 1 YES b2 = 1 YES Write FFh
NO
while b7 = 1
NO
Program Complete
If b4 = 0, Program completed
Read Memory Array Command: - write FFh - one or more data reads from other blocks
Read data from another block
Write D0h
Write FFh
Program Continues
Read Data
Program Erase Resume Command: - write D0h to resume erasure - if the program operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase Suspend command was not issued).
AI00612
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Figure 23. Block Erase Flowchart and Pseudo Code
Start
Write 20h
Write Block Address & D0h
Erase Command: - write 20h - write Block Address (A11-A18) & D0h (memory enters read status state after the Erase command)
Read Status Register
NO Suspend
YES
do: - read status register (E or G must be toggled) if Erase command given execute suspend erase loop while b7 = 1
b7 = 1
NO
Suspend Loop
YES b3 = 0 YES b4 and b5 =1 NO b5 = 0 YES b1 = 0 YES End
AI03851
NO
VPP Invalid Error (1)
If b3 = 1, VPP invalid error: - error handler
YES
Command Sequence Error
If b4, b5 = 1, Command Sequence error: - error handler
NO
Erase Error (1)
If b5 = 1, Erase error: - error handler
NO
Erase to Protected Block Error
If b1 = 1, Erase to Protected Block Error: - error handler
Note: 1. If an error is found, the Status Register must be cleared before further P/E operations.
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Figure 24. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Write 70h
Program/Erase Suspend Command: - write B0h - write 70h do: - read status register
Read Status Register
b7 = 1 YES b6 = 1 YES Write FFh
NO
while b7 = 1
NO
Erase Complete
If b6 = 0, Erase completed
Read Memory Array command: - write FFh - one or more data reads from other blocks
Read data from another block or Program
Write D0h
Write FFh
Erase Continues
Read Data
Program/Erase Resume command: - write D0h to resume the Erase operation - if the Program operation completed then this is not necessary. The device returns to Read mode as normal (as if the Program/Erase suspend was not issued).
AI00615
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Figure 25. Unlock Device and Change Tuning Protection Code Flowchart
Reset Add: don't care Data: 0xFFh TUNING PROTECTION UNLOCK SEQUENCE Issue Read command 5th: Write Cycle
Device locked by tuning code
Add: don't care Data: 0x78h
1st: Write Cycle
Add: don't care Data: 0x48h
6th: Write Cycle
Add: 0x00000h Data: First 32 bit
2nd: Write Cycle (old code, factory setup = 0xFFFFh)
Add: 0x00000h Data: First 32 bit
7th: Write Cycle (new code)
Add: don't care Data: 0xFFh Issue Read command
b7 = 1 YES Add: don't care Data: 0x78h 3rd: Write Cycle
b7 = 1 YES Add: don't care Data: 0x48h 8th: Write Cycle
Add: 0x00001h Data: Second 32 bit
4th: Write Cycle (old code, factory setup = 0xFFFFh)
Add: 0x00001h Data: Second 32 bit
9th: Write Cycle (new code)
b7 = 1 YES Read Status Register
b7 = 1 YES Reset
NO DEVICE LOCKED
b0 = 1 YES DEVICE UNLOCKED
Device locked by new code
AI04501
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Figure 26. Unlock Device and Program a Tuning Protected Block Flowchart
Reset Add: don't care Data: 0xFFh TUNING PROTECTION UNLOCK SEQUENCE Issue Read command 5th: Write Cycle
Device locked by tuning code
Add: don't care Data: 0x78h
1st: Write Cycle
Add: don't care Data: 0x40h
6th: Write Cycle
Add: 0x00000h Data: First 32 bit
2nd: Write Cycle (First part of the tuning code)
Add: location to prog. 7th: Write Cycle Data: data to prog.
Add: don't care Data: 0xFFh Issue Read command
b7 = 1 YES Add: don't care Data: 0x78h 3rd: Write Cycle
b7 = 1 YES Status Register check
Add: 0x00001h Data: Second 32 bit
4th: Write Cycle (Second part of the tuning code)
Location programmed
b7 = 1 YES Read Status Register
NO DEVICE LOCKED
b0 = 1 YES DEVICE UNLOCKED
AI04502
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M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
Figure 27. Unlock Device and Erase a Tuning Protected Block Flowchart
Reset Add: don't care Data: 0xFFh TUNING PROTECTION UNLOCK SEQUENCE Issue Read command 5th: Write Cycle
Device locked by tuning code
Add: don't care Data: 0x78h
1st: Write Cycle
Add: don't care Data: 0x20h
6th: Write Cycle
Add: 0x00000h Data: First 32 bit
2nd: Write Cycle (First part of the tuning code)
Add: block to erase Data: 0xD0h
7th: Write Cycle
Add: don't care Data: 0xFFh Issue Read command
b7 = 1 YES Add: don't care Data: 0x78h 3rd: Write Cycle
b7 = 1 YES Status Register check
Add: 0x00001h Data: Second 32 bit
4th: Write Cycle (Second part of the tuning code)
Block Erased
b7 = 1 YES Read Status Register
NO DEVICE LOCKED
b0 = 1 YES DEVICE UNLOCKED
AI04502
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Figure 28. Power-up Sequence to Burst the Flash
Power-up or Reset
Asynchronous Read
BCR bit 15 = '1'
Write 60h command
Set Burst Configuration Register Command: - write 60h - write 03h and BCR on A15-A0
Write 03h with A15-A0 BCR inputs
Synchronous Read
BCR bit 15 = '0' BCR bit 14-bit 0 = '1'
AI03834
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Figure 29. Command Interface and Program Erase Controller Flowchart (a)
WAIT FOR COMMAND WRITE
90h YES READ ELEC. SIGNATURE
NO
READ ARRAY
98h YES READ CFI
NO D
70h YES READ STATUS
NO
20h YES ERASE SET-UP
NO
40h YES
NO
ERASE COMMAND ERROR
NO
D0h YES A
PROGRAM SET-UP
50h YES
NO E
C
CLEAR STATUS
D
READ STATUS
B
AI03835
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M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
Figure 30. Command Interface and Program Erase Controller Flowchart (b)
E
48h YES TP PROGRAM SET_UP
NO
78h YES
NO
F
TP UNLOCK SET_UP
60h YES
NO
FFh G SET BCR SET_UP YES
NO
03h YES
NO
D
AI03836
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M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
Figure 31. Command Interface and Program Erase Controller Flowchart (c)
B
A
ERASE YES READY NO NO READ STATUS
B0h YES
ERASE SUSPEND
YES
READY NO
NO
ERASE SUSPENDED YES
READ STATUS
READ STATUS
YES
70h NO YES PROGRAM SET_UP C YES READ STATUS
40h NO READ ARRAY NO
D0h
AI03837
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Figure 32. Command Interface and Program Erase Controller Flowchart (d)
B
C
PROGRAM
YES
READY NO NO READ STATUS
B0h YES
PROGRAM SUSPEND
YES
READY NO
NO
PROGRAM SUSPENDED YES
READ STATUS
READ STATUS
YES
70h NO
READ ARRAY
NO
D0h
YES
READ STATUS
AI03838
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Figure 33. Command Interface and Program Erase Controller Flowchart (e)
B
F
TP PROGRAM
YES
READY
NO
READ STATUS
B
G
TP UNLOCK
YES
READY
NO
READ STATUS
AI03839
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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